Modern integrated circuits include a very large amount of logic circuits such as flip-flops, logic gates and the like. These circuits are tested in various manners, in order to provide an indication about the functionality of the integrated circuit.
Integrated circuit designers are forced to use relatively limited resources (such as dedicated test pins, silicone footprint) in order to perform complex tests.
One common method for checking an integrated circuit involves connecting multiple scan logic circuits in a serial manner, such as to form a very long scan chain. A typical scan logic circuit can operate in a functional mode and in scan mode. In scan mode scan data propagates along the scan chain, from one scan logic circuit to another scan logic circuit. In functional mode data propagates between logic circuits in paths that differ from the scan data paths.
Signals, such as clock signals and data signals propagate differently during scan mode and functional mode, as they travel through different paths. A clock signal can be skewed and even dramatically skewed in one mode while being substantially un-skewed in the other operational mode.
Clock skews can cause timing violations such as setup or hold violations. These violations can cause scan data to be corrupted and even force a scan logic circuit to enter an unknown logical state.
A race (also referred to as a race condition) occurs when the timing differences between clock signals that arrive to different components results in timing violations, and especially when a certain scan flip flop samples irrelevant information. A race condition is illustrated in FIG. 1 and FIG. 2.
FIG. 1 is a schematic diagram of prior art flip flops 10 and 30 and of logic 50. During a functional (also referred to as normal or no scan) mode data that is outputted from launch flip flop 10 passes through logic 50 before being received by capture flip flop 30. During a scan mode a scan data signal is sent directly from launch flip flop 10 to capture flip flop 30.
Launch flip flop 10 includes scan data input 11, data input 12, clock input 13, scan enable input 14, first transfer gate (TG1) 15, second transfer gate (TG2) 16, third transfer gate (TG3) 17, master latch 18, first inverter (I1) 19, fourth transfer gate (TG4) 20, slave latch 21 and second inverter (I2) 22. Master latch 18 is a master latch of launch flip flop 10. Slave latch 21 is a slave latch of launch flip flop 10.
Each transfer gate out of transfer gates 15, 16, 17 and 20 has non-inverted and inverted control inputs and first and second terminals. Signals received by the non-inverted and inverted control inputs are complements of each other. When the non-inverted control input has a predefined value a conductive path is formed between the first and second terminals of the transfer gate. For simplicity of explanation only the non-inverted control inputs are illustrated.
The first terminal of first transfer gate 15 is coupled to scan data (SD) input 11. The second terminal of first transfer gate 15 and a second terminal of second transfer gate 16 are coupled to a first terminal of third transfer gate 17. The first terminal of second transfer gate 16 is coupled to data input (D) 12. The second terminal of third transfer gate 17 is coupled to an input terminal of master latch 17. An output terminal of master latch 17 is coupled to an input of first inverter 18. An output of first inverter 18 is coupled to a first terminal of fourth transfer gate 19. A second terminal of fourth transfer gate 19 is coupled to an input terminal of slave latch 20. An output terminal of slave latch 20 is coupled to an input of second inverter 21. The output of second inverter 21 forms the output of first launch flip flop 10.
A non-inverted control gate of first transfer gate 15 receives scan enable signal (Se) from scan enable (Se) input 14. The non-inverted control gate of second transfer gate 16 receives an inverted scan enable signal (Sel). The non-inverted control gate of third transfer gate 16 receives a first clock signal (CLK1) from clock input 13. The non-inverted control gate of fourth transfer gate 19 receives an inverted first clock signal (CLKI1). For simplicity of explanation the inversion of various signals are not shown.
During scan mode, scan enable signal Se is high, causing first transfer gate 15 to conduct and cause second transfer gate 16 not to conduct. Accordingly, scan data from scan data input 11 is provided to the first terminal of third transfer gate 17. Third transfer gate 17 is conductive and fourth transfer gate 20 is not conductive during a first portion of a cycle of first clock signal CLK1. Accordingly, scan data is latched into master latch 18 during the first portion of the cycle of the first clock signal CLK1.
Third transfer gate 17 is not conductive and fourth transfer gate 20 is not conductive during a second portion of the cycle of first clock signal CLK1. Accordingly, scan data that was previously latched into master latch 18 is being latched into slave latch 21 during the second portion of the cycle of the first clock signal CLK1.
Capture flip flop 30 includes scan data input 31, data input 32, clock input 33, scan enable input 34, fifth transfer gate (TG5) 35, sixth transfer gate (TG6) 36, seventh transfer gate (TG7) 37, master latch 38, third inverter (I3) 39, eighth transfer gate (TG8) 40, slave latch 41 and fourth inverter (I4) 42. Master latch 38 is a master latch of capture flip flop 30. Slave latch 41 is a slave latch of capture flip flop 30.
Each transfer gate out of transfer gates 35, 36, 37 and 40 has non-inverted and inverted control inputs and first and second terminals. Signals received by the non-inverted and inverted control inputs are complements of each other. When the non-inverted control input has a predefined value a conductive path is formed between the first and second terminals of the transfer gate.
The first terminal of fifth transfer gate 35 is coupled to scan data input 11. The second terminal of fifth transfer gate 35 and a second terminal of sixth transfer gate 36 are coupled to a first terminal of seventh transfer gate 37. The first terminal of sixth transfer gate 36 is coupled to data input 32. The second terminal of seventh transfer gate 37 is coupled to an input terminal of master latch 38. An output terminal of master latch 38 is coupled to an input of third inverter 39. An output of third inverter 39 is coupled to a first terminal of eighth transfer gate 40. A second terminal of eighth transfer gate 40 is coupled to an input terminal of slave latch 41. An output terminal of slave latch 41 is coupled to an input of second inverter 21. The output of fourth inverter 42 forms the output of capture flip flop 30.
The non-inverted control gate of fifth transfer gate 35 receives scan enable signal Se from scan enable input 34. The non-inverted control gate of sixth transfer gate 36 receives an inverted scan enable signal Sel. The non-inverted control gate of seventh transfer gate 37 receives a second clock signal CLK2 from clock input 33. The non-inverted control gate of eighth transfer gate 40 receives an inverted second clock signal CLKI2. For simplicity of explanation the inversion of the second clock signal and the scan enable signal are not shown.
During scan mode, scan enable signal Se is high, causing fifth transfer gate 35 to conduct and causing sixth transfer gate 36 not to conduct. Accordingly, scan data (previously stored at launch flip flop 10) from scan data input 31 is provided to the first terminal of seventh transfer gate 37. Seventh transfer gate 37 is conductive and eighth transfer gate 40 is not conductive during a first portion of a cycle of second clock signal CLK2. Accordingly, scan data is latched into master latch 38 during the first portion of the cycle of the second clock signal CLK2.
Seventh transfer gate 37 is not conductive and eighth transfer gate 40 is not conductive during a second portion of the cycle of second clock signal CLK2. Accordingly, scan data that was previously latched into master latch 38 is being latched into slave latch 41 during the second portion of the cycle of the second clock signal CLK2.
A timing difference (also known as skew) can exist between first clock signal CLK1 and second clock signal CLK2. This timing difference can cause a so-called race between launch flip flop 10 and capture flip flop 30. FIG. 2 illustrates an occurrence of a race.
Ideally, first and second clock signals CLK1 and CLK2 are mutually synchronized. In practice, and is illustrated in FIG. 2, a timing difference DT 70 exists between these clock signals. Due to timing difference DT 70 cycle 50 of first clock signal CLK1 ends (at point in time 56) during first portion 62 of cycle 60 of second clock signal CLK2. Between the end (point in time 56) of cycle 60 of first clock signal CLK1 and the end (point in time 63) of first portion 62 of cycle 60 of second clock signal CLK2 both latches (slave latch 21 of launch flip flop 10 and master latch 38 of capture flip flop 30) are opened. Because these flip flops are concurrently open a scan data signal can pass (during the same cycle of first clock signal) from master latch 18 to master latch 38. Thus, an older signal latched in launch flip flop 10 is not latched in capture flip flop 30. The state of slave latch 21 is illustrated by graph 72. The state of master latch 38 is illustrated by graph 74. These graphs illustrate possible values of scan data at the input of each of the respective flip flops 10 and 30. It is noted that a latch is deemed to be gated if is prevented (conveniently by a transfer gate that precedes that latch) from receiving new scan data. A latch is deemed to be open if it can receive scan data (for example—the transfer gate that preceded the latch is conductive).
Race condition can be prevented by adding a delay circuit between launch flip flop 10 and capture flip flop 30, usually done by inserting additional delay cells (buffers, etc). Such a delay is area and power consuming.
There is a need to provide a system and method that can prevent race condition.